This project combines analog circuit design and CAD to produce digital circuits that can operate at substantially reduced voltages, which will result in lower power consumption. The project has introduced the QuadRail logic family, which allows voltage control of transistor thresholds to maintain constant logic thresholds. Use of this family permits lower supply voltages because of the tighter control of device thresholds. However, use of this family requires optimization of individual digital cells, new device layout methods, and new strategies for floorplanning, placement, and routing. The research in this project is exploring all of these optimization areas, and is producing a battery powered demonstration system for speech signal processing.

Agency
National Science Foundation (NSF)
Institute
Division of Experimental and Integrative Activities (EIA)
Application #
9408457
Program Officer
Michael Foster
Project Start
Project End
Budget Start
1994-08-01
Budget End
1998-07-31
Support Year
Fiscal Year
1994
Total Cost
$854,000
Indirect Cost
Name
Carnegie-Mellon University
Department
Type
DUNS #
City
Pittsburgh
State
PA
Country
United States
Zip Code
15213