This project is designing an architecture and compiler for video signal processing, with collaboration among researchers in computer architecture, compilers, and signal processing. The architecture is a very long instruction word machine dedicated to the applications, which means that a large number of small data paths are used. Address generation may receive hardware support. The compiler differs in several ways from general purpose compilers: optimization is sought even at the cost of high compilation times, and memory usage will be explicitly optimized. Architecture and compiler design are being evaluated by experimentation with application codes, including video compression, image enhancement, and machine vision. The architecture is being simulated on a network of high-performance workstations, while the compiler is being constructed based on the Gnu C compiler. The architecture and compiler will be iteratively improved to result in a high- performance system and a set of design principles.
