This research is on models and tools for the design of board-level digital systems. Research includes: (1) Developing a formal specification language for board-level systems based on well defined building blocks, where some of the building blocks are very complex, such as microprocessors. In building the language, only a few critical component types, including programmable parts, are being represented rather than representing all possible parts. (2) Finding simplified models for the board specification and verification processes. The use of hierarchy in the verification process is being explored through specifying the actual behavior of an implementation as well as the desired behavior of the system. Algorithms for timing relationships are being examined also. (3) Algorithms for layout problems, particularly hierarchal compaction of circuit layouts and the interaction of placement and detailed routing, are being investigated. This grant is made under the Faculty Awards for Women Scientists and Engineers Program.
