This Small Business Technology Transfer (STTR) Phase II research project aims to introduce a series of instruments to the microelectronics industry that allow rapid, high resolution residual stress inspection, defect location and quantification. In silicon wafer manufacture, small cracks may appear at the beginning of the wafer process and must be located to avoid adding value to damaged wafers. In semiconductor wafer bonding, de-bond defects may result from trapped dust particles and gas bubbles resulting in reliability and performance degradation. The infrared grey-field polariscope was able to locate these defects and quantify the residual stress state using a laboratory-based system. Now, this technology will be interfaced with optimized detectors to improve defect resolution and introduced onto a microscope platform to improve inspection of smaller defects. Finally, these stress analysis tools will be integrated into an automated inspection system that will be applicable to on-line inspection of the above-mentioned defects.
The profitability of many devices and processes can be significantly hindered by low process yields. Yields can be improved with process control tools that catch stress variations immediately, and customer satisfaction and device reliability improvements made by implementing affordable 100% inspection to eliminate all damaged devices. In addition to making our nation's microelectronics industry more competitive, this tool will advance the state of scientific knowledge by improving resolution limits and provide quantitative measurements for researchers who study semiconductor substrates, wafer bonding, MEMS and integrated circuits.
