This SBIR Phase II research project intends to demonstrate a unique circuit method for GHz clock distribution inside CMOS chips, which provides state-of-the-art performance and is modular, scalable, and reusable. The theoretical foundation of this technology is the Bi-Directional Signaling (BDS) principle implemented over on-chip transmission lines. The project covers the design, fabrication, and evaluation of a comprehensive test chip aimed at validating key aspects of this new method such as the practical accuracy of a long distribution system, the realization of inexpensive high-quality integrated transmission lines, and the design of low power high precision active circuits for local clock generation. If laboratory tests confirm the expected performance and features, this method will be the basis of a valuable new VLSI Very Large Scale Integration (VLSI) technology.
The demonstration of scalable and reusable circuit Intellectual Property (IP) for clock distribution will cause a major simplification in the VLSI design methodology with substantial benefits to the manufacturers of integrated circuits. The semiconductor industry will be able to produce faster processing, lower power, and lower cost VLSI components for systems such as computers and communication devices.
The main objective of this SBIR phase-2 program was the validation of MHI’s BDS concept for GHz clock distribution and other GHz phase-synchronization applications in large silicon chips. To this end, we developed original circuit solutions and designed a test chip in mainstream TSMC 0.18 mm CMOS technology. The test chip was fabricated and packaged through the MOSIS Service. Lab evaluation of this test chip showed that a 2 GHz signal was distributed synchronously to multiple points along a 1.8 cm passive bus containing narrow transmission lines. At every clocking point a small active circuit extracted a globally phase-synchronous local clock signal. Despite natural signal skew and loss over long transmission lines, the phase alignment errors of the distributed signals were estimated at less than 2% of signal period, and the relative magnitude errors at less than 1 dB. The transmission lines were implemented with two top metal layers (Al). The total width of the passive bus was less than 30 microns. The active circuits extracting the synchronous local clocks required less than 1 mA from the 1.8 V power supply to generate a few hundred mV output signals when 500 mV p-p signals were applied at the input of the transmission lines.
