This Small Business Innovation Research (SBIR) Phase I project aims to demonstrate the feasibility of rapid in-line detection of visible (macro) defects on wafers in semiconductor industry. The semiconductor manufacturing industry is a major contributor to the U.S. economy. Chips produced by this industry are used in a broad range of devices including PC's and cell phones. There are about 500 processing steps involved in fabrication of a typical chip using dozens of processing equipment. Defects may be introduced anywhere in the processing chain. This project catch large (macro) defects that are visible to human eye as soon as they occur. The idea uses off-the-shelf scanner technology but sophisticated image processing algorithms to detect and classify such faults and identify remedies to fix the faulty equipment right away before any further processing. This approach will significantly reduce costs and increase the output of fabs by minimizing the production of bad chips. This equipment can be inserted throughout the fabrication plant and catches faults without disrupting wafer processing. Wide adoption of this technology can provide significant savings and provide the U.S. semiconductor industry with a competitive advantage.
The commercial potential of this project is enabling widespread adoption of macro-defect detection at every step and every wafer in semiconductor manufacturing. There is substantial potential in the semiconductor industry for an inexpensive tool for real-time detection of macro defects right at the equipment where the defect is generated. The successful commercialization of the proposed defect detection tool will assist in significantly increasing manufacturing yields and thus lowering costs. The global semiconductor defect-detection market has experienced significant growth over the past decade with the total market for automated test equipment expected to exceed $2 billion in 2010. This product will find use in several other secondary markets such as MEMS, solar energy devices, LED, photonics, etc. Finally, microelectronics affects almost every aspect of our lives. Hence, a product that makes a significant contribution to lowering the cost of manufacturing ICs will positively affect the society at large.
This Small Business Innovation Research Phase I project has demonstrated the feasibility of a novel tool for automatic detection of macro defects on semiconductor wafers based on optical scanning. This tool is intended for use in fabs that manufacture Integrated Circuit (IC) chips for personal computers, laptops, cellular phones, etc. Integrated circuits are mass-produced from large (12 inch) silicon wafers that undergo many different fabrication steps. During each of these wafer processing steps, defects may form due to particle contamination, film thickness variations, dislocations, scratches, cracks, etc. The size of these defects range from that comparable to the critical dimensions of the integrated circuits (30-50 nanometer) to those that are almost visually detectable (100-500 micrometer), to large defects that may span several dies on the wafer. Many of these defects eventually become "killer defects," i.e., defects resulting in the die failing final electrical tests (electrical short resulting in chip failure). With an increase in the number and complexity of processes involved in IC fabrication, it is of critical importance to detect macro defects early in the manufacturing process cycle. Additionally, more ICs will pass the final test if such detection is performed for each and every wafer without adversely affecting the factory output of the manufacturing process. SC Solutions, a leader in providing advanced sensing, control, and signal processing solutions to the semiconductor industry, has demonstrated feasibility of a macro-defect detection tool that satisfies these industry needs with its innovative in-line technique to rapidly detect defects on whole wafers using a combination of inexpensive scanning hardware and sophisticated software algorithms that can be readily integrated into existing wafer processing equipment. In this Phase I research, three tasks were completed that successfully demonstrate feasibility of a macro-defect detection tool. The first task involved the development of algorithms and software for defect detection: We have developed fast detection algorithms for wafer orientation and die location. In addition, we have developed fast algorithms for detection of defective dies, based on detection of a reference die. Finally, we have also developed algorithms to classify defects in different patterns, such as circular defects, defect clusters, and individual specs. The second task involved the development of a preliminary hardware/software tool prototype: We selected, characterized and compared two off-the-shelf high-resolution optical scanners, and integrated our software algorithms with these scanners to establish a preliminary tool prototype. We developed a preliminary Graphical User Interface (GUI) to facilitate visualization of the results. The third task involved a feasibility demonstration on actual test wafers: We were able to demonstrate feasibility of our scanning and defect detection on multiple wafers that were processed by our industrial partner. The results are extremely promising and provide a path for continued development of the product in Phase II. In summary, SC Solutions has conclusively demonstrated the feasibility of implementing macro-defect detection using inexpensive commercial-off-the-shelf hardware combined with sophisticated algorithms in this NSF Phase I research project. Using off-the-shelf hardware we were able to scan high-quality images that could be processed with our algorithms to produce very reliable detection of macro defects. We tested our algorithms on actual fab wafers from our industrial partner, and the results were extremely promising; a defect-free wafer was processed without any false positives, and on a scratched wafer we were able to identify all the scratches at the exact locations of the scratches. Our industrial partner has been very pleased with our progress in Phase I as we have exceeded all their expectations. We believe our results are a significant advancement in the state of the art in rapid in-line detection of visual defects. The next critical step is to carry out the Phase II R&D effort to develop a commercial hardware and software prototype defect detection tool ready for integration into commercial equipment. There is substantial potential in the semiconductor industry for an inexpensive tool for real-time detection of macro defects right at the equipment where the defect is generated. The successful commercialization of the proposed defect detection tool will assist in significantly increasing manufacturing yields and thus lowering costs for the semiconductor industry. The product will find use in several secondary markets such as MEMS, solar energy devices, LED, photonics, etc. Finally, microelectronics affects almost every aspect of our lives. Hence, a product that makes a significant contribution to lowering the cost of manufacturing ICs will positively affect the society at large.
