This Small Business Innovation Research (SBIR) Phase I project proposes to develop a revolutionary, yet simple and well-designed technique for the cost effective deposition of compound semiconductor epitaxial material mesa arrays on large (300mm) silicon wafers. The subsequent processing steps integrate smoothly with silicon CMOS (Complementary Metal-Oxide-Semiconductor) processing similar to the current SiGe (Silicon Germanium) BiCMOS (Bipolar CMOS) technology. Previous attempts at the integration of III-V materials with silicon have had limited success due to many factors including high cost, CMOS incompatibility, small wafer size, and a lack of technological and market readiness. In contrast, the proposed solution is very cost effective, and it builds on recent technological progress in advanced materials deposition and handling. The vehicle chosen for the demonstration of this technology is the fabrication of high speed VCSEL (Vertical Cavity Surface Emitting Laser) arrays on silicon. The immediate application is in high speed interconnects for computer systems and peripherals including next generation USB (Universal Serial Bus) cables.
The broader impact/commercial potential of this project lies in the following aspects: This technology can merge the advanced compound semiconductor materials with the superior processing and efficiency of silicon ICs. This will end years of isolated development and will bring new electronic and optoelectronic device capabilities to mainstream silicon processing. In electronics applications, high speed and high power transistors based on InP, and GaN device technologies will be processed with silicon CMOS on large wafers. This will integrate advanced analog and power functions with silicon CMOS based control and processing. In addition, it will offer an alternative route for the continuation of performance enhancement in silicon ICs independent of feature size reduction. In optoelectronics, the integration of GaAs and InP based optical emitters and receivers on silicon will allow the miniaturization and cost reduction of optical transmitter and receiver modules. The seamless integration of optical and electronic functions on silicon chips will lead to faster interconnects and will significantly reduce the cost per bit in fiber optic signal transmission.
Semiconductor manufacturers are being driven to ever higher levels of integration, which, up to now, has meant scaling of the core technology (e.g. CMOS) and expansion of the chip size. One need that has not been sufficiently addressed is the ability to enhance performance and/or functionality by wafer-level integration of compound semiconductor materials and structures. Such integration could further reduce the number of chips required in cell phone handsets and mobile computing devices, for example. Photonic interconnects for a new generation of computers is probably the most important application of the proposed epitaxial transfer technology - however, it also has the potential for new applications and technologies because the cost-effective, intimate integration of complex epitaxial structures and devices with Si-based electronics can solve technical problems that neither microelectronics nor conventional III-V technology could handle alone. There is an on-chip hybrid material synergy that opens up new functionality and higher levels of performance. In Phase I Oepic demonstrated the feasibility of a novel approach to realizing III-V on Si, the epitaxial mesa array transfer (EMAT) process. The principal innovation in this process is the expansion step that occurs between the release of the epitaxial mesas and the subsequent bonding of the mesas to a Si wafer (Figure 1). This step enables major cost-savings over the current state-of-the-art, principally by recovery of the substrate and the ability to populate large Si wafers with small amounts of unprocessed or partially processed III-V wafers. This, in turn, sets the stage for the low-cost mating of compound semiconductors with industry standard Si CMOS. Specifically, in Phase I we selected a commercially available dicing tape for the expansion. We developed a set of masks to test mesa formation and release. We grew an epitaxial test structure on a 3" GaAs substrate. We developed a process to release the epi and recover the substrate. We developed a process to transfer the epi to tape. We successfully demonstrated expansion of the epitaxial mesas on tape with an expansion factor of 3X (Figure 2). This will allow the transfer of an epitaxial array from a single III-V substrate to a full size silicon wafer. We studied the epi quality after expansion and found it to be excellent. We studied bonding alternatives and determined the likeliest path for the next demonstration phase. Finally, we outlined a plan for epitaxial transfer to Si in a CMOS-compatible fashion. We believe these results to be extremely encouraging and that they justify the continuation of this effort. The application of this technology to optoelectronic interconnects from the micron to the meter scale has potential far reaching implications for society and the world. The first is that, as short reach communications transitions from copper to waveguide, the amount of power consumed will drop dramatically. This will provide significant energy savings over current and future server and cloud computing requirements, which in turn will reduce society’s dependence on fossil fuels and alleviate global warming. A similar opportunity exists at the chip-to-chip communications level. If, for example, the backplane can be replaced by low-cost, high-bandwidth free-space optical interconnects, the cooling requirements will drop dramatically and the energy budget for servers will shrink. Moreover, innovative chip-to-chip optical communications will enable the growth of multi-core architectures allowing computing power to reach the scale necessary for, for example, more accurate weather prediction and modeling and predicting complex biological systems. Finally, as photonic interconnects penetrate the core, Moore’s law will be extended beyond the limits of copper interconnects, creating performance benefits for everything from portable computing to supercomputing, and enabling such life-enhancing applications as artificial vision.
