This Small Business Innovation Research (SBIR) Phase II project aims to demonstrate a high-performance spin torque magnetoresistive random access memory (ST-MRAM). ST-MRAM technology promises a powerful combination of non-volatility, high density, high speed, and low power. The major impediment to commercializing ST-MRAM has been that the write current for programming the magnetic tunnel junction (MTJ) bits are too large. Large write current can cause tunnel barrier breakdown, thereby compromising memory reliability. Additionally, large write current requires large select transistors beneath each bit, preventing high density. In Phase I project, an MTJ bit design with a low enough write current has been successfully demonstrated. In this Phase II project, a large, high-density ST-MRAM demonstration circuit will be developed using this improved bit design. Several novel circuit design approaches that have potential for higher speed, higher density and lower power will be evaluated. The circuit will provide the bit statistics needed to optimize the bit design and enhance the yield to the level required for a highly reliable commercial ST-MRAM.
The broader/commercial impacts of this project will be the potential to enable the commercial applications of ST-MRAM. The Toggle MRAM is already finding many applications in the stand-alone memory market including networking, industrial controls, data server systems, military, aerospace industry etc. However, in order for MRAM to achieve its full commercial potential, higher density and lower power consumption are needed. High density translates to lower cost. Reducing power consumption is increasingly valued in areas such as portable electronics or even enterprise computing. ST-MRAM technology has the potential to meet these needs by combining non-volatility, high density, high speed, low power, unlimited endurance, and scalability in a single memory.
Magnetoresistive Random Access Memory (MRAM) is a nonvolatile memory technology with unlimited endurance and RAM characteristics that distinguish it from other nonvolatile technologies such as Flash or EEPROM. Everspin Technologies is currently shipping a family of MRAM products based on Toggle-mode switching with densities ranging from 256 kb to 16 Mb. The overall goal of this SBIR program was to develop a new MRAM product based on spin-torque switching (ST-MRAM), that will enable higher memory densities and higher performance. Successful commercial development of ST-MRAM would vastly expand the number of applications that would benefit from MRAM technology by pushing into applications currently addressed by DRAM. The primary technical challenge to a functional ST-MRAM was to reduce the spin-torque switching current density (Jc). Reducing the Jc has two major benefits: preventing tunnel barrier damage or breakdown by lowering the switching voltage Vsw, and minimizing the size of the pass transistor in the CMOS below the bit. In Phase-I, we demonstrated improvements to the magnetic tunnel junction (MTJ) device that enable lower write currents and greater separation between the write and breakdown voltages. These improvements were critical for the development of a practical ST-MRAM technology since they improve the endurance/reliability of the memory array and reduce the size of the transistor needed in each memory cell. In addition, since the completion of Phase-I, we developed a simplified structure that provides the benefits obtained in Phase-I, but was easier to pattern and more manufacturable. The goal of Phase-II was to demonstrate a working ST-MRAM circuit incorporating unique Everspin memory design concepts and bit cell that would show the capability of our ST-MRAM technology to replace DRAM. Everspin met all the major objectives of this NSF Phase-II SBIR. We produced a fully functional ST-MRAM 16Mb demonstration circuit which helped to enable a commercial 64Mb ST-MRAM with a DDR3 interface. The 16Mb ST-MRAM design test vehicle (DTV) was successfully designed, simulated, taped-out, and processed. We then evaluated the write and read performance of the DTV in detail and verified that all aspects of the circuit met the expected performance. Optimization of the material stack over the course of the project allowed us to write and read the full 16Mb array at nanosecond time scales with near zero errors. A novel free layer was developed using a CoFeB-based alloy, resulting in an improvement of more than 50% in the voltage write window for error-free programming, and a reduction of the programming error-rate of almost 100X. Further optimization of this free layer reduced the switching voltage (Vsw) to tunnel barrier breakdown voltage (Vbd ) ratio so that Vsw/Vbd≈0.3, while maintaining an energy barrier for data retention of Eb≈80kbT. We also made a number of improvements to the material stack that increased the magnetoresistance (MR) from 69% to 111%, and reduced the number of extrinsic bits with low breakdown voltage Vbd by more than 100X. The changes to the MTJ stack included optimization of the MgO tunnel barrier oxidation, the CoFeB-based free layer, and the fixed layer. In addition, we refined the fabrication process of the ST-MRAM arrays by optimizing the photolithography for patterning the bits. We achieved a more uniform distribution of bit shapes in the array, as evidenced by a reduction in the relative distributions of both bit resistance Rmin and bit switching field Hsw. The results of all this effort significantly helped Everspin to develop a fully functional 64Mb DDR3 ST-MRAM built on 90nm CMOS technology that is currently being sampled to customers. We have run standard memory tests, such as a March6N pattern, on the full 64Mb at 800MHz with 0 fails for greater than 105 cycles. Full functionality was also verified from 0ºC to 70ºC with no significant change in performance. These results indicate excellent potential for introduction of a commercial ST-MRAM product and were reported in more detail during an invited talk at the recent 2012 joint MMM-Intermag conference, as well as in a corresponding paper "A Fully Functional 64 Mb DDR3 ST-MRAM Built on 90 nm CMOS Technology", IEEE Trans. Magn. 49, 4441 (2013).
