This Small Business Innovation Research Phase I project attempts to overcome fundamental limitations that are currently inhibiting the realization of much needed low-cost high-performance digital-to-analog converters (DACs), which can accommodate the wide bandwidths of current and future communication systems, software-defined-radios (SDR), and a wide range of other applications. The focus of this research is the development of circuitry and signal processing and control algorithms that would effectively address impairments experienced in a complementary-metal-oxide-semiconductor (CMOS) implementation of a novel DAC topology designed to accommodate ultra-wide bandwidths. While the CMOS fabrication process may be tailored for digital processors and memory, it is a most challenging environment for the design of high-performance, wide dynamic range analog circuitry. The solutions being developed essentially provide the DAC with ?self-healing? capabilities that allow it to overcome inevitable impairments such as device mismatches, non-linearities, and timing misalignments. Preliminary results indicate the validity of the proposed architectures and approaches and it is anticipated that a fabrication-ready design will result from the Phase 1 research. The involvement of researchers and PhD candidates from academia in this research allows them exposure into most challenging research topics that are of great interest to the semiconductor industry.
The broader impact/commercial potential of this project is in allowing ultra-high-performance data-conversion capabilities to be integrated into low-cost CMOS system-on-chip (SoC) solutions that are widely used in commercial applications of various types ranging from communications and multimedia to instrumentation. In particular, the technology being developed will allow for the integration and low-cost realization of this most critical function in a true SDR. The proposed innovation, targeting the self-sufficient-compensation for the effects of inevitable impairments, such as fabrication-process variations, mismatches, non-linearities, and timing misalignments, through the employment of novel built-in calibration and compensation circuitry and algorithms, will allow integrated DACs to deliver ultra-high performance (e.g., 16-bit resolution at rates above 10GHz) without requiring costly testing at fabrication, production-yield losses, laser trimming, or any other consequence of traditional design and manufacturing of high-performance analog integrated circuits. The approach to be developed has a broader impact on chip manufacturing, as these impairments represent limiting factors in other functions as well. As an enabling technology, the proposed innovation can potentially greatly increase the size of the existing market for data converters, currently at $3B, and allow for various new consumer applications where wide bandwidths of operation are needed and cost is a constraint.
The objective of this Phase I research project was to develop a manufactureable solution for an ultra-wideband digital-to-analog converter (DAC), which represents a key enabling technology in various existing and emerging markets. The novel DAC architecture will be manufactureable in low-cost advanced CMOS processes, where it can be integrated within various system-on-chip (SoC) designs, while exhibiting high performance in terms of bandwidth and resolution. Such low-cost integrated DAC represents a critical building block in applications such as wideband communication systems, radar systems, imaging for medical and security applications, and instrumentation. Using a combination of digital computations and analog circuitry, with emphasis on extensive digital signal processing, the high performance DAC self-sufficiently overcomes various inevitable impairments that are expected in fabrication, such as device mismatches, parasitic effects and non-linearities. This allows for high production yield, low cost digital testing, and the elimination of costly trimming procedures currently practiced in the production of high performance data converters. The Phase 1 research resulted in the identification and modeling of the relevant impairments and in the development of solutions, both at the circuit level and at the algorithmic level, for built-in measurement and calibration techniques. The accomplishment of these objectives involved surveying existing solutions and relevant literature, modeling of the DAC core and its non-idealities, algorithm development, circuit design, and the fabrication of a test-chip and a printed-circuit board (PCB) for the evaluation of its performance. The targeted ultra-wide bandwidth for the DAC provides it with the capability to simultaneously support all bands of long-term evolution (LTE) 4th generation cellular base-stations. This allows LTE-Advanced systems to concurrently place multiple simultaneous RF carriers at the required frequencies from 700 MHz to 2.7 GHz and thus eliminate the need for multiple quadrature modulators and separate DACs, which are currently required for non-contiguous carrier aggregation, i.e. reduce the number of transmitter lineups required to aggregate carriers from different bands. An additional important advantage offered by this technology is the ability to synthesize ultra-wide bandwidth complex signals for use in phased array radars and in instrumentation. An important part of a built-in self-compensation scheme is the built-in measurement mechanism that provides a sufficiently accurate measurement of the parameter or impairment that is to be compensated or adjusted. Various novel ideas, for which patent filing is being pursued, have been conceived for this function as well, allowing for sufficiently accurate measurements to be performed self-sufficiently, while maintaining overall low-cost realization and testing for the wideband DAC. As an enabling technology, the proposed innovation can potentially greatly increase the size of the existing market for data converters, currently at $3B, and allow for various new consumer applications where wide bandwidths of operation are needed and cost is a constraint. The preliminary results of this research, as well as initial discussions with industry leaders, has provided Xtendwave with indications confirming that such technology can represent a critical differentiator. Hence, Xtendwave envisions that valuable intellectual property developed throughout this project may be licensed or sold, without necessarily requiring that a fabricated IC be offered by the company. The involvement of PhD candidates from The Ohio State University, a sub-awardee of this grant, in this research provided them exposure into most challenging research topics that are of great interest to the semiconductor industry.
