This Small Business Innovation Research (SBIR) Phase I project targets high-performance clocks to be implemented in a standard silicon CMOS process to address ever-growing demand for a higher level of integration resulting in a product smaller feature size and power savings for mobile and other consumer electronics applications by replacing multiple crystal oscillators (XTAL's). For all silicon CMOS (Si-CMOS) oscillators their accuracy is primarily limited by aging that causes frequency to shift every year by a certain amount. Depending on the application total elimination or mitigation of aging technologies will be developed. The project's key innovations are in self-calibration algorithms for aging elimination and analog aging compensation schemes maintaining acceptable complexity. The project will involve research and development using a board-level prototype as well as feasibility study for an IC implementation minimizing the system's cost and its power consumption. The proposed innovation practically eliminates aging for mobile-phones and GPS devices and first time allows a Si-CMOS clock to achieve an accuracy of single ppms, so far reserved to temperature compensated crystal oscillators (TCXO's). It is anticipated that this technology will result in critically needed frequency-accuracy enhancements ranging from a factor of 2 to 10, compared to currently available Si-CMOS oscillators.
The broader impact/commercial potential of this project stems from the fact that oscillators are essential components for all consumer electronics and communications as well as for computer and networking markets. In 2007, 10 billion XTAL and other oscillators were manufactured worldwide reaching $3.6 B Total Available Market (TAM). The emerging Si-CMOS and the Micro-machined Electro-Mechanical Systems (MEMS) oscillator segments target portable applications, such as PDAs, camcorders, and MP3 players, where the size and degree of integration is key. The global market for MEMS/Si CMOS oscillators will grow from $5.2 M in 2008 to $217 M in 2013 with an Average Annual Growth Rate (AAGR) of 125%. The aging elimination and mitigation technologies developed in this project are applicable in microprocessors, memories and communication systems. Societal benefits include the much-needed increased accuracy, and a timely low-cost solution for Si-CMOS oscillators, providing a cost-effective alternative to XTAL oscillators. The improved clock accuracies and their ability to be integrated on large System-on-Chips (SoC's) will enable developing more compact products with power consumption savings, battery life extension and added functionality to a greater portion of the population at reduced costs and will also serve to foster remote education, telecommuting and e-commerce.
The first main objective of this research was to verify through circuit simulations the proposed methods of mitigation aging effects in all-CMOS oscillators. This task was performed in collaboration with University of Texas at Dallas (UTD). The second main task was to develop calibration algorithms for aging free oscillator. The next two tasks were to design and build a discrete prototype of an aging free oscillator and to practically test the calibration algorithms estimating the prototype frequency accuracy and its phase-noise performance. Apart from first task all other tasks were performed entirely in-house by SyncRef. Simultaneously, a significant part of first task was performed by SyncRef PI in collaboration with UTD. The overall research results are encouraging. The simulations confirmed our hypothesis that using simple circuit design techniques will mitigate the frequency shift caused by aging effects related to hot carrier electrons. Additionally, two methods to accommodate temperature variations in connection with aging were investigated. First method was not practical since it introduced additional parasitic that substantially shifted the frequency. The second method proved to be practical. Simulations confirmed that using that method leads to reducing frequency variation. Despite changing the original assumptions the frequency stabilization method is compatible with aging mitigation and guarantees that aging effects will be mitigated. In the area of calibration algorithms, substantial progress was achieved. Several algorithms were developed and initially tested including 3 different modes of operation involving distinct functionality and different hardware configurations. The mobile application radio reference was modeled by an accurate XTAL. By using this reference, precise calibration and tuning can be demonstrated. An accurate reference will allow for self-calibration, while operating the VCO. However, due to a short time of the study, the effects aging may not influenced VCO performance. Therefore, for the purpose of testing, self-calibration will be implemented by artificially disturbing the tuning voltage values and correcting for any VCO performance changes. For all temperature points used in calibration, the voltage supply is held at its nominal value. The evaluation board design and development required substantial effort, but the overall result was very good. Compared to the previous evaluation board design, the new design and its layout substantially improved. The main improvements resulted in reducing the noise levels, EM pickup and cross-talk. Additionally, the new design eliminated several bugs and inconsistencies in evaluation-board connections. Also, it solved the difficult mounting problem for a critical component – a VCO. The task of programming the evaluation board was very involved. It involved FPGA, USB, serial interfaces, and micro controller programming. Additionally, a PC based GUI (graphical user interface) was developed. To prove the board functionality, the FPGA have been carefully programmed and tested. The evaluation board is now ready for systematic testing aimed in evaluating its frequency-stability over temperature performance. This task will be performed with constant updating and fine-tuning the calibration algorithms. The current Phase I grant gave SyncRef an enormous opportunity to develop and test new ideas and build an evaluation-board prototype to be used in presentations for prospective customers and investors. This activity is a critical effort by SyncRef in its attempt to commercialize its technology. We hope it will build a lot of confidence with our technology and it will allow us to enter partnerships with large semiconductor vendors delivering chips to mobile OEMs. Also, it will help us obtain funding from even most demanding professional investors. In today’s tough early stage investment environment, developing a working prototype gives a SyncRef a clear advantage over its peers, who very often have to resort to simulations and Power Point presentations. Work will continue on the with the evaluation board to improve its performance and to create an intuitive and user friendly interface allowing our customers to familiarize themselves with our technology and its unique advantages and features. With such a vehicle SyncRef’s chances to commercialize its technology grow substantially and will strengthen our technology presentation strategy for Phase II proposal. 12.00
