Modern digital chips that are used in a myriad of commercial and consumer electronic products, are very complex and currently consume significant amounts of power. According to the International Energy Agency, energy consumed by information and communications technologies as well as consumer electronics will double by 2022 and triple by 2030 to 1,700 terawatt hours. It is thus imperative to devise effective new CAD tools based on new algorithmic paradigms to design digital chips so that they consume as little power as possible (without degrading performance). The benefits of this will include lowering the power consumed off the power grid (environmentally friendlier products), smaller energy costs for cooling high end systems like high-performance servers, and longer battery lives for portable devices (e.g., smart phones, laptops) and implantable medical devices. In the crucial physical synthesis (PS) stage, of the chip design flow (the sequence of stages that the chip design goes through), certain transformations are applied to the circuit so that the metric of interest (e.g., power) is optimized subject to constraints on several other metrics (e.g., speed, yield, chip area/cost, temperature). In conventional industry design methodology, these transforms are applied sequentially, and each transform is applied sequentially across circuit components, which result in sub-optimal designs (e.g., higher power consumption). The team has developed a novel PS tool called DNF-PS which simultaneously applies any desired set of transforms accurately and also does so simultaneously across the entire circuit in order to optimize power, while satisfying multiple constraints. DNF-PS is thus much more effective than current industry and academic tools.
The goal of this project is to explore and strengthen opportunities for commercializing DNF-PS via: 1) Learning about and refining the commercial aspects of the plan. 2) Further strengthening the performance and quality of DNF via a few more technological advances, part of which could be spurred by the customer discovery and interaction aspect of the I-Corps program. The commercial area of the DNF-PS tool is the well-established market of Electronic Design Automation (EDA), and the potential customers of the proposed product are well known: chip design / semiconductor companies. The merit of this activity will have the following components: a) Design of enhanced algorithms to improve the near-optimality properties of DNF-PS (thereby resulting in reducing power consumption even further), thus making it even more attractive for industry use. b) Developing divide-and-conquer strategies in DNF-PS that can intelligently partition very large designs into more manageable chunks, and optimize each separately (thus being more runtime efficient) without compromising power optimization. c) Getting customer feedback on DNF-PS and gathering market intelligence on the value of such a tool and its market requirements. The broader impact of this proposal will include: a) Highly power optimal chips can be designed efficiently with DNF-PS, with the obvious attendant improvements in the battery life and/or energy footprint of many thousands of electronic products. b) Furthermore, due to the significant efficacy of the underlying DNF optimization technology, DNF-PS can lead to a significant jump in chip design quality in other metrics besides power, like speed, reliability and chip yield. This can benefit various applications areas in which these metrics are paramount (e.g., reliability is very important in automotive, airplane and space electronics) and also reduce chip cost (due to increased chip yield).
In past research in our lab at the University of Illinois at Chicago, we developed a novel physical-synthesis tool (which is an important phase in the chip design flow) called DNF-PS which simultaneously applies any desired set of transforms, and also does so simultaneously across the entire circuit in order to optimize power, while satisfying multiple constraints. DNF-PS is thus much more effective than current industry and academic tools which mostly apply these transforms sequentially, and each is also applied sequentially across the circuit. For example, compared to one of the best tools in the market, DNF-PS has demonstrated significant power reductions of 14-20% over and above that obtained by that tool for a number of benchmark and industry designs without degrading performance. Chip-design tools such as DNF-PS and its competitors belong to the electronic design automation (EDA) market. The main goal of this project is to explore and strengthen opportunities for commercializing DNF-PS by interviewing industry experts, including potential customers (chip design companies), and determining from them the following: a) whether, in their estimation, DNF-PS can add value to their current chip-design flow; b) whether their company could buy this product, and if so, what they were willing to pay for it, and c) what improvements they would like to see in DNF-PS. The NSF I-Corps project consists of two workshops at the beginning and end of an approximately 6-7 week period. Our team, consisting of the standard PI, Entrepreneurial Lead (EL) and Mentor, was able to complete the first workshop. Both the EL and Mentor were from outside UIC by the time the project started, and due to other interests they had, they decided not to to pursue the I-Corps program beyond the 1st workshop. We could thus only complete the 1st 3-day workshop held in July 2012 at Georgia Tech, Atlanta. I will describe the outcomes of attending this workshop below. Besides attending courses at this workshop, we conducted extensive interviews with at least 11 technology experts (eight of them during the workshop, at least two before it, and one after it) drawn from a broad spectrum of careers in the high-technology world in general and also in EDA. These included current or past entrepreneurs in the high-tech industry, engineers, management and salesmen in the EDA and chip-design industry. The main conclusions that we reached on the aforementioned questions based on these interviews are: a) DNF-PS’s power optimization is excellent and would add significant value to any chip-design flow, especially since low-power chip design is very important and has strong demand in the current environment of battery-powered devices and green-technology. b) Chip-design companies would most likely buy this product after some runtime improvements were made (see next item), and could pay approximately $100,000 for it per year. c) It would be very useful to reduce DNF-PS’s runtime by a factor of about 5, as runtime of tools is a major issue with chip-design engineers. While we unfortunately could not complete the entire period of this project, as mentioned above (we returned the remainder of the funding after meeting the expenses related to the 1st workshop for all team members), the above conclusions gleaned from the interviews are promising, and we are currently working on significantly reducing the run-time of DNF-PS.
