This Small Business Innovation Research Phase I project proposes to replace Cu on-chip interconnects with a graphene technology. Nanoscale Cu interconnects that make electrical connections to active devices, mainly transistors, are an essential component of nearly all semiconductor chips. In Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs), this Cu interconnect fabric is applied as a separate component to the transistors that are embedded in the Si wafer. As the dimensions of these transistors are continually scaled down to improve performance (a trend that major chip manufacturers agree will continue for the next few decades), the Cu interconnect fabric must also be scaled in parallel. Whereas transistors improve performance with scaling, the electrical resistance of Cu interconnects rapidly increases when scaled due to intrinsic properties of the metal. This brings an abundance of interconnect pain points to chip manufacturers, limiting their competitive edge for high-performance and low-power processors. This project develops graphene on-chip interconnects that can replace Cu and facilitate future IC scaling.
The broader impact/commercial potential of this project is the enabling of a tremendously diverse portfolio of technologies including, but not limited to, mobile computing / smartphones, implantable biomedical devices, and hybrid engine controllers and semiconductor chips cross-pollinate well into broad commercial applications. Scaling the dimensions of transistors and interconnects has defined the success that microelectronics (and now nanoelectronics) have enjoyed for nearly half a century. Technologies that facilitate continued scaling and keeping pace with Moore's Law are a must for chip manufacturers to maintain a competitive edge. With scaling comes faster performance, expanded capabilities, and greater reliability to all of the diverse applications that are driven by such chip technology.
This NSF Phase I SBIR project focused on the development of a Complementary Metal-Oxide-Semiconductor (CMOS) compatible process for fabricating graphene on-chip interconnects. This patented technology will displace the current copper (Cu) damascene process that forms the interconnects of nearly every CMOS chipset sold today. As the global semiconductor market moves forward, Cu interconnects limit both the power consumption and scalability of CMOS chipsets. Through this project, fundamental advancements have been made to the understanding of processing and manipulating carbon nanomaterials. The introduction of graphene into mainstream CMOS processing will allow a backlogged wealth of novel and disruptive device designs to find application in consumer electronics, medical devices, and space systems. The outcomes of this Phase I project include the development of Harper’s Graphene Local On-Chip (GLO) process. This process is based on Chemical Vapor Deposition (CVD) graphene and is capable of supporting interconnects on the 200-450mm wafers used by high-volume CMOS foundries. In addition to this, the value proposition for GLO as a low-power back-end-of-the-line (BEOL) for Advanced RISC Machines (ARMs) and as a scalable BEOL for high-performance Central Processing Units (CPUs) was benchmarked via physics-based models. Beachhead market segments for low-power ARMS in automotive body electronics and device-side cloud computing were identified. Secondary market segments in data processing and server-side cloud computing were also identified. Successful introduction of graphene into CMOS processing in Phase II is disruptive, far reaching, and has the ability to change the basis of competition in the global semiconductor industry.
