This Small Business Technology Transfer (STTR) Phase I project addresses one of the key roadblocks for Silicon Carbide (SiC) power MOSFET technology. SiC power MOSFETs have huge potential of increasing efficiency and reducing cost of power converters due to superior material properties of SiC. Unfortunately, they have not fulfilled their potential due to high channel resistance and instability of threshold voltage. These limitations are primarily due to poor quality of the interface between SiC and silicon dioxide. State-of-the-art gate oxide formation processes achieve moderate channel mobility and demonstrate instability of threshold voltage. The objective of this research is to develop an alternate gate oxide processing technique that will achieve significantly higher channel mobility while eliminating the instabilities. Initial studies will focus on test structures to study potential techniques and to gain understanding into the mechanism that cause poor mobility and instability. Once the most promising technique is identified and optimized, it will be used to fabricate SiC power MOSFETs. With higher channel mobility and stable threshold voltage, this new process is expected to enable SiC power MOSFET technology that will result in cheaper and more compact power converters with higher efficiency compared to today's power systems.
The broader impact/commercial potential of this project is quite far reaching for power converters which are a critical component in many systems like the photovoltaic inverter, electric inverter, motor drives, etc. Existing converters use silicon IGBTs which have high switching losses. SiC MOSFETs have significantly lower switching losses compared to silicon IGBTs but currently available SiC MOSFETs are too expensive and their reliability has not been proven yet. This project can realize reliable and affordable SiC power MOSFETs. Lower losses of SiC MOSFET result in power converters with higher efficiency. Due to lower switching losses, SiC MOSFETs will also enable higher frequency power conversion which results in more compact power converters that need less material for other passive components. Lower losses also result into less heat generation and reduction in cooling costs in a system. Overall, this will reduce the cost of power converters. Lower losses and cheaper, compact power converters will particularly benefit renewable energy generation and electric vehicles resulting in direct reduction of greenhouse gas emission and associated benefits to the society.
Project goals: Wide bandgap power devices such as SiC power MOSFETs show great promise to meet the burgeoning need for higher efficiency and increased power density of stationary and mobile power electronics applications, including datacenters, solar inverters and hybrid and all-electric vehicles. However, the performance of SiC power MOSFETs have yet to achieve their entitlement performance due to the relatively poor inversion-layer electron mobility of the SiC MOS channel. In previous work, channel mobility improvements have been demonstrated to the channel mobility on lateral MOSFET test structures, yet the high-temperature threshold voltage stability was poor. In this Phase I STTR program, the primary objective is to evaluate the capability of various gate oxidation techniques to improve the performance and threshold voltage stability of 1200V SiC MOSFETs. To evaluate the SiC gate oxidation processes in this NSF STTR Phase I program, we fabricated and characterized two lots of full SiC 1200V power DMOSFETs to quantify the on-resistance performance and high-temperature threshold voltage stability. In this program, we fabricated two lots of 1200V SiC power MOSFETs with variations in the gate processing to evaluate gate oxide processing techniques. The devices fabricated under this Phase I STTR program were processed at Cornell Nanofabrication Facility (CNF) using the processes and designs developed by Monolith Semiconductor. A selection of the SiC DMOS gate oxidation process splits processed through the gate oxide steps at Auburn University, with the majority of the processing performed by Monolith Semi at CNF. Devices were then electrically characterized on-wafer for on-resistance and threshold voltage stability. Key outcomes: Evaluation on full SiC DMOSFETs is required to evaluate new gate oxidation processes: As suggested by the reviewers to our proposal, we confirmed that it is important to evaluate gate oxidation techniques on p-well regions with heavy-doping that are suitable for SiC power MOSFETs. For example, we achieved a peak mobility of 35 cm2/V-s for the thin-PSG on SiC power MOSFET p-wells, half the value observed on lightly-doped p-type layers. This indicates that lightly-doped lateral MOSFETs give indications of channel improvements, but cannot predict the final mobility observed in SiC DMOSFETs. For this reason, it is important to perform development on full SiC DMOSFETs. While this reduced the number of lot iterations we could perform, this was an extremely productive suggestion by the reviewers. Phosphorus diffusion significantly reduces on-resistance but incurs threshold instability and low yield: We evaluated phosphorus diffusion processes using two techniques. The "Thin-PSG" showed the lowest on-resistance at room temperature of all samples (5.6 mOhm-cm2), but has unacceptable threshold voltage stability (a large ΔVT of 7 Volts at 225°C). While the on-resistance performance of the phosphorus diffusion samples is impressive, the poor threshold voltage stability is unacceptable. Based on these results, we at Monolith Semi believe there is no further opportunity to eliminate the poor yield and unacceptable threshold stability of the phosphorus diffusion approach. We demonstrated NO-like performance by using Monolith Semi’s approach: In the NSF Lot #2 we demonstrated a modified gate oxidation technique that demonstrated the same high-temperature on-resistance performance as the baseline NO sample. Monolith Semi’s gate oxidation process demonstrate acceptable high-temperature threshold voltage stability: Auburn University characterized a selection of SiC power MOSFETs with the various process splits. We tested devices at 225°C, well beyond the stress in most applications (typically < 175°C), and above the rating of currently available commercial devices (150-200°C). First, the transfer characteristics were measured at room temperature. We stressed the gates first at VGS=+15V at 225°C, cooled under bias and re-measured the transfer characteristics. Next, samples were then stressed at VGS=-15V at 225°C and cooled and the transfer characteristics were re-measured. The threshold voltage shift was determined by the difference in threshold voltage before and after that stress test. The devices were stressed for 5 minutes and 60 minutes to determine the impact of stress duration on the threshold voltage shift. The "Thin-PSG" sample showed a large positive and negative threshold instability of 4 and -7 V, respectively. This device turned normally-on after the negative stress conditions, even for the a stress duration of only 5 minutes. This threshold instability is unacceptable for commercial devices. In contrast, Monolith Semi’s samples showed good threshold voltage stability of < 1V. There was no change in the threshold voltage shift between 5 and 60 minutes stress duration. Monolith Semi’s process show threshold voltage stability superior to commercially-available SiC power MOSFETs (+1/-3V shifts at 225°C). This shows that the Monolith Semi process prevents the large instability induced by the phosphorus-diffusion approach. Thus this new gate oxidation process can achieve the threshold-voltage stability required for reliable, high-temperature operation. These results measured at 225°C is especially important since it exceeds the current state of art, and will enable development of high-temperature power electronic devices for high-temperature applications, such as electric vehicles.
