Researchers have developed large-scale Field Programmable Analog Arrays (FPAA) that enable products requiring ultra-low-power computation and computing within a programmable and configurable framework. This project plans to use the FPAA ICs to demonstrate core signal processing functionality for widespread use and begin the process of iterating and getting feedback regarding performance, power levels and features.

The potential impact from the FPAA ICs could empower a range of electronic devices and require a factor of 1000 times less power consumption than current digital approaches. This approach could enable a wide-spread change in low-power electronics. An additional impact from this technology will create an ecosystem for additional technological growth, in a range of applications spaces, empowered by programmable and configurable analog ICs eliminating the need for highly costly process of custom analog IC design, fabrication, and testing. This approach enables a range of new approaches to be realized, many applications not even envisioned.

Project Report

The MAVRIC team began the NSF iCorps program in April 2013 with the explicit goal of identifying a technology market fit for Dr. Hasler’s neural integrated circuit research. At a high level, we understood that the technology could deliver several orders of magnitude in power efficiency for a broad range of recognition applications. We understood that the programmable nature of the technology meant that a single circuit design could be reprogrammed to a large number of end customer applications. We understood there was value in being able to integrate the entire analog signal chain from the sensor backwards because this meant implementations would be compact. However, we didn’t know was "who cares?" Based on Steve Blank’s Lean Startup methodology, the iCorps program emphasized the importance of "getting out of the building" and talking with prospects/partners to validate hypothesis about multiple aspects of the business model. Initially we identified three target markets: Internet-of-Things (IoT) Edge node infrastructure, Portable Medical Electronics, and Wearable Computing. The iCorp process exposed high customer interest in neural classifier applications, particularly in the area of wearable computing, making progress to the next level of customer engagement dependent upon showing physical results demonstrating ultra-low power classification. Wearable devices require ultra-low power devices, often with massive context-aware computing, that need to perform in the noisy real world; a large gap exists between consumer expectation and what can be realized using conventional circuit techniques. We ultimately executed a "pivot" and focused on the Wearable segment. Having now conducted over 100 field interviews, we found four strong value propositions for the Wearable Computing market. Wearable computing encompasses electronics that are worn by a person to integrate computing into daily life or work. The market is experiencing rapid growth, and is considered the next big thing to follow the smartphone revolution. Press activity around wearable technology has been considerable: "augmented reality" goggles and glasses for both gaming and professional applications, and popular wrist-band/pedometer monitoring products. This premise was validated in discussions with over 80 commercial representatives. We believe we can address this need at far lower power and cost, making it an ideal entry point for the technology. Mavric’s disruptive technology uses a combination of ultra-high energy efficient (10MMAC/uW or x1,000 more efficient than custom digital) configurable analog computation with even more efficient neurally based physical classification (4 to 10GMAC/uW or x1,000,000) performing very high performance embedded decision and control structures. The solution is in two areas for speech, vision, and communication applications, first in highly energy and area efficient configurable analog + digital devices, and second in biologically faithful models of temporal classifiers integrated into a configurable architecture. A factor of 1000 improvement in power efficiently is roughly equivalent to the improvement seen from the start of DSP (1978) to the digital energy efficiency wall of 10MMACs/mW. Our classifier approach is based upon neuromorphic design, where recent approaches have shown a technology roadmap to build human level cortex [1] at similar biological power levels as part of our key technology foundation. It has already been shown that certain functions such as Matrix Multiplication, Frequency decomposition, Adaptive filtering and Winner Take All, are a factor of 1000x more efficient than digital processing. [1] J. Hasler and B. Marr B, "Finding a roadmap to achieve large neuromorphic hardware systems,'' Front. Neurosci 7:118, 2013.

National Science Foundation (NSF)
Division of Industrial Innovation and Partnerships (IIP)
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Rathindra DasGupta
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Georgia Tech Research Corporation
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