This project focuses on the development of a complier that automatically performs correct and efficient memory management. The compiler automatically manages the data of the application on a multi-core architecture that does not provide any memory management in hardware. Such architectures are scalable (i.e., processors with hundreds and thousands of cores can be designed), and are more power-efficient. This compiler does this through application analysis. It analyzes each kind of code/data (i.e., code, stack data, heap data and global variables) and inserts data management instructions in the application, so that the application can execute correctly and efficiently on many-core processors that will not have any support for memory management in hardware.
This compiler may be needed by system development companies that are developing relatively high-performance computing systems, for example, 3D scanner, high capacity 3D printers, TVs, audio video processing in cars etc. All these companies may want to use the processor with best performance and lowest power. However, top of the line processors will soon not have support for memory management in hardware, and the existing applications will not compile them. This compiler may have the ability to enable them to utilize the power and performance of the latest many-core processor for their systems. To the end user, they receive a power-efficient product with higher performance. Hand-held devices thus developed, while providing improved performance, will be lighter and will require fewer recharges.
