Emerging Digital Signal Processing (DSP) VLSI products are widening the horizons of system designers. Because of their compact size and low cost, tightly-coupled single-board multiprocessor configurations are now quite feasible. This research examines the degree to which hardware can be minimized by judicious selection of an architecture that lends itself to modern Very Long Instruction Word (VLIW) compilation techniques. With the need to solve DSP problems in mind, the architectural tradeoffs are being determined for a small number of critical DSP routines involving FFT's, 2D filtering, and dynamic programming algorithms. Also, automatic instruction scheduling/compaction techniques are being related to the architectural choices. Ultimately, it is expected that the results generated will highlight the strengths and weaknesses for some of the commercially- available DSP chips. Reviewers awarded this very high scores of 16, 18 and 18. All reviewers saw this as quality work stemming from innovative ideas to be done by an excellent group. There is high potential for a Phase II project. Success will lead to a meaningful advance in the theory and practice of instruments that require signal processing circuit design.
