To build fast inexpensive artificial neural network hardware, a high-performance but compact synapse circuit is required. Digital implementations require large synapse circuits. Existing analog synapse designs are highly non-linear or require expensive fabrication processes. The proposal is to develop, simulate, layout, and fabricate a new linear synapse circuit during Phase I. The new linear synapse circuit is small, allows for on-chip learning, and uses standard CMOS bulk technology and so resulting neural network chips can be fabricated inexpensively by many vendors. The circuit density improvement could be more than 100 over existing circuit design.
