The proposed correlator chip is intended for the two main application areas in radio astronomy: cross-correlation spectroscopy in aperture synthesis arrays and autocorrelation spectroscopy at cm and mm wavelengths. The objectives of Phase I are to design, simulate, and layout a CMOS digital correlator chip with the following characteristics: a) 1 GHz sample rate, b) 10 channels, c) 2-bit (four-level) quantization, and d) 32-bit counter/accumulator. It has already been demonstrated experimentally that the 1 GHz sampling rate can be achieved with a combination of systolic architecture, novel pipeline differential logic circuits, and a 1.0 um CMOS fabrication process. The objectives of Phase II are to increase the number of channels per chip to 100 while maintaining the 1 GHz clock frequency and the 4-level quantization scheme. Provision will also be made for a number of features such as 1-bit correlation for solar burst observation, blanking of correlation coefficients for pulsar observations, and phase switch mode. The commercial market for correlator chips is estimated at two to five million dollars in 1992 and it will grow 15% to 20% annually. Presently, most digital correlator chips are designed by each radio astronomy laboratory for their own internal use. The performance- to-cost ratio of the proposed correlator chip will be up to 10 times higher than that of existing correlators.
