This Small Business Innovation Research Phase I project's goal is to establish the feasibility of an automated design rule generator to optimize the manufacturability of state-of-the-art electronic chip designs. The need for this tool is enhanced by recent developments in lithography, which suggest that it may be possible to reliably build chips with very small feature sizes. To achieve the goals of the proposed research will require the development of a database environment that encodes geometric similarity of features on chips consistent with hierarchical CAD designs. An analysis of the database to derive equivalency classes on which to generalize rules obtained from prototype studies, whether they be heuristic, experimental, or model-based. In Phase I, the feasibility of this approach will be demonstrated through application to prototypical designs. This tool will greatly expand the existing market for chip redesign software because it will allow fast, cost effective full chip redesign and optimization to enhance manufacturing yield. The market for this new product is estimated to be $20 million today and grow at the rate of 20-30% per year.
