This project is investigating MOS data acquisition circuits. The research is directed toward establishing the fundamental factors which limit the performance of MOS analog-digital interface circuits, and toward synthesizing architectures which closely approach those fundamental limits. Specific topics for investigation include self- calibrated pipelined A/D circuits, video CODEC's, investigation of fundamental performance limits in sample and hold circuits, concurrent analog processing in A/D converters, and mixed-level simulation for A/D interface applications.
