This research is on layout problems in ultra-large-scale- integration (ULSI). The nature of the multichip module (MCM) layout problem and associated design problems are being investigated. Activities include: (1) Exploring MCM layout by characterizing the physical requirements posed by MCM technology. Layout models for the MCM design problem are being built. Physical constraints being included in the model are: functions of layers (signal, power-ground, redistribution), layer ordering, wire width and separation, and grid-gridless geometry. The differences between MCM layout and traditional IC layout are being considered. (2) Finding techniques to decompose a 3-D MCM layout problem into a set of single layer layout problems. (3) Designing efficient algorithms for the MCM layout problem and incorporating performance requirements into the algorithms. Layer minimization, performance and global routing are being addressed.
