This award provides partial funding for a workshop to access current state-of-the-art schemes for implementation of high- performance parallel machines. For large high-speed parallel systems, the problems facing the computer designer must be addressed from both the architecture and the interconnection perspective. Machine and packaging engineers must work in concert in order to identify and solve the issues pertaining to clock distribution, routing, and partitioning before the hardware layout is done. The effects of interconnects and packaging on parallelism and clock speed are evaluated. Also, the workshop addresses subjects related to board, chip area constraints, signal degradation, electromagnetic modeling and simulation of interconnects, CAD simulation, optical computing, and their effect on machine performance. Workshop areas include microelectronics packaging, optoelectronics, machine architecture, processor design, VLSI, and CAD with topics grouped into one of three areas: (1) Electronics Packaging and Interconnects; (2) Optoelectronics and Optical Technologies; (3) Machine Architecture.
