An architecture is presented that unifies fine-grain control-flow and data-flow dependences in the context of contemporary superscalar processors, preserving highly streamlined mechanisms of superscalar processors while endowing them with dataflow properties. Future independent instructions are fetched, executed, and locally finalized, their results propagated and corresponding resources freed, and their cumulative effects sustained regardless of prior unresolved branch mispredictions. Branch mispredictions no longer serialize execution, leaving exceptions and finite resources as the only remaining serializing constraints in the system.
In the domain of high-performance microprocessors (which power supercomputers, personal computers, laptops, and even cell phones), there remain a few dogged bottlenecks that fundamentally constrain performance, making it difficult to translate the potential of additional transistors into effective performance gains. The project's broader significance is an approach that aims to overcome one of the remaining grand-challenge problems in scaling microprocessor performance.
