Networks-on-chip (NoCs) are an on-chip interconnection fabric of choice for general-purpose chip multiprocessors and application-specific multiprocessor systems-on-chip. This project focuses on network-on-chip modeling and optimization to enable early-stage design exploration that fully elaborates the achievable envelope of NoC power, area, speed, reliability and cost. An architectural estimation thrust develops new architecture-level estimation methods that are portable to different router microarchitectures and that can accurately capture implementation effects. The thrust addresses the automatic generation of architectural estimation models, the modeling of chip design implementation flow choices and their impacts, and new trace-aware and workload-dependent estimations. An architectural optimization thrust develops new methodologies for trace-driven optimization of router configurations, packet routing and network topology, with consideration of runtime network resource contentions.
Successful completion of this project will help network-on-chip and multiprocessor system-on-chip designers reduce design effort while improving chip area, delay and power metrics. This will be enabling to the efficient design of more complex, higher-functionality integrated-circuit products within given cost and power limits. The research will also produce software tools to establish a foundation for further work by other research groups. Through research participation, both graduate and undergraduate students will be trained in this emerging aspect of system-on-chip design.