The goal is to use parallel computers to generate tests for VLSI circuits whose complexity makes conventional test generation techniques costly in terms of computation time. A parallel implementation scheme for representation and manipulation of vectors is being created to provide a uniform basis for development of various vector test generation techniques. Theoretical studies as well as implementation are being used to evaluate alternatives. Approaches ranging from tree- embedding procedures to macro-based techniques to fault simulation based methods are being investigated to provide a comparative basis for the various approaches. The implementation of the approach is efficient and is being done on conventional vector machines as well as distributed memory multi-processors. New approaches to VLSI testing need to be developed in order to thoroughly test complex, high transistor count IC's. The research investigates the use of parallel computers to efficiently generate test vector sets. The approach is unique in that several test generation approaches, both traditional and novel, will be compared to assess the effectiveness of using parallel computers in reducing IC test time. The principal investigator is a promising and competent young professor who should make a significant contributions to the field.
