Similar to logic devices, flash memories based on extended floating gate are scaling down following Moore's Law and running into limit at about 45nm technology node because of the tunneling oxide thickness scaling limit. We propose to use hetero-nanocrystals to replace the extended silicon layer as a floating gate for nonvolatile applications beyond the 45nm technology node. The important reason behind the utilization of the hetero-nanocrystal floating gate is that hetero-nanocrystals can introduce a deeper well with an additional barrier for long-retention charge storage and keep fast writing/erasing speed at lower operation voltage in a scaled device. Through this exploratory research project, we will prove the scalability of hetero-nanocrystal memory toward CMOS ultimate limit. The specific plan is 1) to simulate scaled memory devices containing dot variations using 3-D NEMO codes to prove that the same number of charges and the collective effect of these charges rather than dot density/size variation play dominant role in determining device performance across a wafer, and 2) to experimentally conduct self-assembled growth of silicon dots onto small SiO2/Si patterns with dimensions corresponding to beyond-45nm scaled technology nodes to achieve well-controlled dot statistics. The resources from the PI's Quantum Structures Laboratory, the PI's ongoing collaboration, and the university's new nanofabrication facility are ready to be used to explore these goals. This research will enrich the state-of-the-art knowledge on nanostructures and help to discover more principles of the bottom-up nanofabrication technique: Self-assembly. In addition, the incorporation of hetero-nanocrystals into MOSFET memory devices will also enrich the knowledge of nanoelectronic devices. It will help to explain the unusual electrical transport characteristics in hetero-nanostructures. Finally, the project will also add to the core knowledge of the technologically important material systems of silicon and silicide.
Broader Impact: The proposed work on the scalability of hetero-nanocrystal memories, if successfully demonstrated, will extend the nonvolatile memory scaling limits and be used by the electronic memory industry to produce better devices than present commercialized ones to benefit people's daily lives. The net benefit to memory companies and civilians will be tremendous, beyond the point (compared with present nonvolatile memory of more than $10 billion market) that could be estimated. The project will also train a graduate student to gain valued experiences from memory device simulations to nanofabrication techniques such as self-assembly. To have even broader impact, the PI will disseminate the successful research results to K-12 students through ongoing UCR summer programs in nanotechnology, which are designed to increase the number and diversity of students pursuing studies and careers in science and engineering fields. This can be achieved through a 2-hour lecture to high-school students and middle-school students on nanotechnology and the relationship between memory and cell phones/digital cameras in the end of this project. Moreover, multiple group visits to research laboratory from local school districts will be arranged at the UCR's Chancellor scholarship day. These educational modules will foster science and engineering interest in these K-12 students.
