Title: Ultra Low Energy Computing for Next Generation Implantable Smart Cardiac Pacemakers Project Summary Cardiovascular diseases are one of the major causes of all human deaths. Arrhythmia related human cardiac mortality and morbidity can be reduced by the implantable artificial pacemakers that are designed to monitor the cardiac status and to regulate the beating of the heart. Not many years ago, the functionality of a pacemaker was mostly limited to monitoring signals from the heart and assisting its operation via artificial pacing when any predefined abnormality was detected. Recently, pacemaker manufacturers have started incorporating advanced features to make the pacemaker smarter and more user friendly. With low energy wireless connectivity, the pacemakers can be programmed to automatically activate alerts to the cardiologist or to the hospital via the connected smart phone or network when an emergency occurs. In the future, the wireless connectivity may also enable the cardiologist to remotely adjust the settings of the pacemaker to address the emergency or to recommend other corrective measures. Unfortunately all the added new features come at the expense of increased power consumption. Also, the wireless connectivity of the implantable devices opens up the possibility of hacking. In the case of pacemakers a hacker will be able to maliciously reprogram the pacemaker. These device security threats lead to the need for secure communication channels. The entire computational task inside a pacemaker is done by a dedicated processor. The upcoming generation of pacemakers is expected to both diversify the processor work-load and demand significantly increased computational capabilities.
This research aims to develop low-energy computation methods and design methodologies that can enable future cardiac pacemakers to become a reality. A novel concept of dynamic computing is developed as a part of this research which will enable the reduction of pacemaker power consumption by detecting and eliminating repetitions of low level arithmetic/logical operations both in software and hardware implementations. By identifying overlapping computational steps and predictable data flow patterns present in most implantable cardiac pacemaker workloads, the proposed design methodologies promise enhanced performance and improvement in battery life. Applicability of the developed techniques will be investigated and tested in the context of pacemaker signal processing, security, and reliability workloads. Nearly 225,000 permanent pacemakers are implanted annually in the United States. The battery in a pacemaker can last 8-10 years and the pacemaker itself is replaced during a surgical procedure. The development of ultra-low energy computing techniques for pacemakers is expected to extend the battery life further, which in turn will reduce the frequency of the surgical procedures needed to replace the pacemaker. The reduced number of surgical procedures will also bring down the associated health care coast. The low energy computing techniques could also enable the future pacemakers to add more advanced features without sacrificing the battery life. .
The development of the next generation of smart pacemakers opens up a new frontier in patient care where the patient is ?connected? to the doctor at all times, but this new added feature comes with a cost in terms of battery life. The proposed research addresses this problem and will enable the realization of smart pacemakers with energy efficiency. Using energy efficient design, if the battery life of the pacemakers can be extended by 10 ? 15%, then the frequency of surgical procedures needed to replace these devices can be reduced proportionally which in turn will reduce the associated healthcare cost.