Whether running on a single cell phone or a conventional PC - all of today's state-of-the-art speech recognizers exist as complex software running on conventional computers. This is profoundly limiting for national and homeland security applications in which mobility or stealth are essential. Today's state-of-the-art speech recognizers fully occupy the resources of a modern desktop PC; but we cannot deploy such hardware in scenarios where size, covertness, long-life, and untethered operation are essential. Our cell phones last a week if we do not use them; they last a few hours when we actually speak to them. To remedy this, we must move the core of today's most successful speech recognition strategies directly into silicon. We propose to design a silicon speech recognition architecture that can offer at least 100 times better energy efficiency than today's software solutions. We will explore performance trade-offs by extending field programmable gate array (FPGA) emulation technology, so that proposed chip designs may be rapidly evaluated executing real-world problems involving hours of voice data. The Carnegie Mellon / Berkeley team brings decades of experience with silicon design, low-power design, and speech recognition to this effort. The goal of the project is to liberate speech recognition from the artificial constraints of its current software-only form, and to make it a reliable, pervasive technology for the field-oriented national and homeland security applications where it is today unsuitable.
