Digital Signal Processing (DSP) workloads are typically numerically intensive, parallelizable, and increasingly required in a number of applications. The project will develop the architecture, algorithms, circuit, chip layout, and software for a single-chip processing system that is capable of calculating DSP workloads with high performance and high energy efficiency. Processing chips contain a very large number of small asynchronously clocked programmable processors connected by a reconfigurable 2-dimensional grid network. The research will result in the design, fabrication, test, and characterization of a prototype processing chip, including the development of software for a small number of complex multi-algorithm applications. The project will evaluate the merits of the proposed architecture for these types of DSP workloads.
The research may lead to new capabilities that were previously constrained by maximum levels of power dissipation or throughput, in numerous applications such as life-extending medical devices, high volume consumer products, and very high throughput radar and image processors.
