Variability is becoming a key concern for micro-architects as technology scaling continues and more and more increasing ill-defined transistors are placed on each die. While in the past it was sufficient for variability to be addressed at the device and circuit levels (and so abstracted away from the micro-architect), we are reaching a point where designers at the micro-architecture level will need to consider the effects of variability or sacrifice larger and larger amounts of yield and/or performance. To address these issues, we propose to develop parameterizable variability models for the most common micro-architecture structures used in high-performance processors, ranging from data-path modules to SRAM and CAM arrays. These variability models can then be used to augment any existing single- or multi-core simulation framework and allow for early identification of which micro-architecture decisions are more likely to exacerbate or filter out unwanted variability effects. The project plans to address these issues by proposing models that micro-architects can work with for both 2D and 3Darchitectures, without having to rely on complex device- or circuit-level variability information. An integral component of the research proposed here is its impact on educational activities of the PI at Carnegie Mellon University, as well as its overall societal impact via enabling frontier application development. In addition to providing a venue for graduate student research, the proposed research is envisioned to be seamlessly integrated with other educational activities, such as undergraduate, graduate, or minority student mentoring and recruiting, as well as course development or revamping to reflect the continuously changing landscape of next generation system design.
