"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."
In the 21st century, the dominant computing platform has shifted to multicore chips that implement cache-coherent shared memory and run multi-threaded applications. Unfortunately, these chips do not provide a deterministic model to either software or hardware developers. Reasoning about and testing for multiple possible executions is much harder than reasoning about and testing for a single correct sequential execution, as was possible under the von Neumann model that dominated in the 20th century. Easing the burden of programming multicore chips is critical to provide society with the rapid, cost-effective performance gains that we have all come to expect. Moreover, broad impact requires practical solutions that do not ask industry to discard or rewrite billions of lines of existing general-purpose thread-based software.
To this end, research under this proposal will develop solutions for managing non-determinism with alterative implementation approaches that provide complementary benefits and opportunities. (1) Work will expand techniques of recording executions for deterministic replay to improve replay parallelism and extend the scope of record/replay to hardware debugging and fault-tolerance. (2) Work will develop and advance a deterministic coherence model that eliminates a major source of non-determinism in shared-memory multiprocessor systems: memory races. (3) Work will develop both all-software and hardware-accelerated implementations of deterministic coherence, in part, through extensions to the Wisconsin GEMS simulation infrastructure. (4) Finally, work will explore rebuilding coherence upon a formal deterministic foundation. Broader impacts will include embodying the proposed work in public software releases (e.g., GEMS) as well as dissemination to students and through courses, talks, industrial affiliates, and commercial influence.
