The objective of this research is to develop techniques that utilize solid-state memory technologies from device, circuit, architecture, and system perspectives across I/O hierarchy in order to exploit their true potential for improving I/O stack performance in high-performance computing systems. The PIs plan to develop I/O friendly memory system architectures to enable hybrid processor-memory 3D integrations with largely reduced off-chip I/O traffic. In addition, adaptive cache management and hotspot prediction methods are being developed to address the low random write performance of solid-state drives, and data processing techniques will be developed to enable run-time configurable trade-offs among solid-state drive performance characteristics. A comprehensive full-system simulation infrastructure is capable to evaluate and demonstrate the research under diverse high-performance computing workloads. The research facilitates the high-performance computing systems to utilize existing/emerging memory and processing technologies to tackle the grand I/O stack design challenge. It can greatly contribute to enabling high-performance computing systems to stay on track of their historic scaling, and hence benefit numerous real-life applications such as biology, chemistry, earth science, health care, etc. This project contributse to the society through engaging under-represented groups, research infrastructure dissemination for education and training, and outreach to high school students.
The objective of this project is to develop techniques that utilize solid-state memory technologies from device, circuit, architecture, and system perspectives across I/O hierarchy in order to exploit their true potential for improving I/O stack performance in high-performance computing systems. Towards this end, we have performed the following investigations: (1) Developing 3D stacked PCM system architecture and optimization techniques; (2) Exploring process variation aware PCM system design techniques; (3) Exploring fast and energy efficient programming techniques for multi-level cell based PCM systems; (4) NV2-SRAM: a versatile non-volatile memory substrate for flexible cache optimizations; and (5) Studying effective storage management in light of heterogeneous storage devices. This research project has produced 9 conference (PACT-09, MICRO-09, DSN-11, HPCA-11, HPCA-13, VEE-13 (a,b), IISWC-13, ICS-14)and 1 journal (IEEE CAL)publications. The graduated students have traveled to the topic conferences to present their work to the research community. Three Ph.D. students and one Master students have participated into this project and have successfully defended their dissertation/thesis based on this research. One of them received the prestigious CI fellowships. A high school student also participated in this research project. Via the REU supplementary grant, an undergraduate student was also involved. This project aims at facilitating the high-performance computing systems to most effectively utilize existing/emerging memory and processing technologies to tackle the grand I/O stack design challenge. It contributes to enabling high-performance computing systems to stay on track of their historic scaling, and hence benefits numerous real-life applications such as biology, chemistry, earth science, health care, etc. This project contributes to the society through engaging under-represented groups, research infrastructure dissemination for education and training, and outreach to high school students.
