The objective of this research is to create a new failure-resistant architecture for high-speed digital links to enable the next generation of high-performance communication and computing systems. The failure-resistant architecture is based on maximum a posteriori (MAP) detection and overcomes not only challenging channel impairments, but also deterministic impairments incurred in the interface and timing circuitry. The system-level protection given by MAP detection offers new opportunities in the design of power-efficient analog-to-digital converters (ADCs) and timing generation based on seas of digital gates that exploit the variations and errors in unreliable, deeply scaled devices. The MAP detector itself is enhanced using an iterative, soft message-passing algorithm to unleash its full throughput potential while providing tolerance against underlying circuit failures.
The new link techniques developed in this research will improve both the computing capability and the energy efficiency of large data centers needed for cloud computing. The techniques also impact personal and mobile computing by delivering more efficient serial links such as the next-generation universal serial bus (USB). The interdisciplinary nature of this project encourages a tight integration of mixed-signal circuits, digital circuits and signal processing research and provides excellent training to students through research and industry internships.
