Rapid technology scaling has fueled an unprecedented growth in the semiconductor industry, transforming the face of modern society. Commodity systems have undergone a sea change from the uniprocessor era of past decades to the current many-core era. With numerous on-chip processing cores, the communication fabric in many-core systems becomes a critical design component. Network-on-Chip (NoC) architectures are widely regarded as the most promising design for the communication platform for many-core systems, primarily due to their scalability. Many-core systems such as Intel 80-core and Tilera have already used NoCs as the backbone of communication between their on-chip processors. To maintain fault-free execution in these many-core systems, it is imperative to ensure sustained lifetime in both NoCs and processing cores. This research embarks on boosting sustainability in NoC architectures through a proactive design paradigm.
Using a cross-layer collaborative venture, spanning from the device layer to the architecture layer, this project establishes a transformative framework to design sustainable NoC architectures. Existing techniques for NoCs tackle the sustainability design challenge in a reactive way by triggering corrective mechanisms after a component failure. The investigators explore an orthogonal proactive strategy, recognizing the need for device level aging awareness during the entire life span of an NoC. This project demonstrates that sustainability can be improved in NoCs without sacrificing power-performance, by considering the criticality of packet transmission. By playing a central role to facilitate long term sustainability in NoCs, this research can substantially improve the cost efficiency in building large data centers supporting our modern compute intensive society. Major research insights will be disseminated through teaching to develop relevant skill sets, lead to more sustainable future computer systems, and benefit the community at large.
