This research addresses the major architectural and technological trade-offs inherent in multiple-bus computer systems. The focus will be on two main issues: (1) analysis of the basic architectural features of multiple-bus systems; and (2) development of new performance models for such systems. Technology-dependent analytical models that account for the loading, crosspoint control, and access arbitration in shared- memory architectures are being developed. The recently introduced crosspoint cache will be further explored. Together with an address-trace generation, parameters are provided in the development and evaluation of a new semi-Markov bus performance model. Efficient reconfiguration strategies for systems with bus failures are also integrated into the performance models.
