This research investigates the generation of manufacturing tests for highly sequential VLSI circuits. The approach is based on combining the best features of deterministic and simulation based techniques. Deterministic techniques are mainly used to (1) identify untestable and redundant faults and (2) to correct the direction of the simulation based search. Simulation based test vector generation examines a set of test vectors to determine a new test sequence to detect some faults. This process, while accurate and fast, generates longer than necessary test vectors. The technique being explored is detecting and correcting the genetic search, using deterministic ATPG. This process involves an intricate exploration of the power of a switch-level logic and fault simulator in an combination with a genetic algorithm and the deterministic ATPG during the test generation process. The technique is being applied to design problems such as, circuit partitioning, initial test set finding, and circuit initialization- structure to determine performance and quality of generated test sets.
