In order for compilers of fine-grain parallel architectures to be as effective as possible, compiler writers must understand the interactions between the phases of the compiler. These phases include instruction scheduling which rearranges code in order to increase available fine-grain parallelism. In addition, code transformations to increase memory performance are applied, such as tiling and loop interchange to increase cache performance, prefetching to prefetch values from memory in order to eliminate the memory latency, and scalar replacement which changes array references to scalar references to decrease memory accesses. The compiler also performs register allocation, which allocates registers to values so as to minimize the number of memory accesses. The goal of this proposed work is to investigate the interactions of these phases. This effort is being undertaken along two directions. The first direction is to continue previous work in cooperative register allocation and instruction scheduling by (1) incorporating cooperative software pipelining and performing the cooperative register allocation and scheduling optimizations over a single framework, the program dependence graph (2) performing a thorough analysis and experimental study of the effects of register assignment strategies on scheduling to increase fine-grain parallelism. The second direction is to investigate the interactions between code transformations improving memory performance and other compiler phases. In particular, the proposed work will investigate (1) the impact of scalar replacement and software prefetching on instruction scheduling to increase fine-grain parallelism and on register allocation (2) strategies for enabling communication between code transformations to increase memory performance, register allocation, and instruction scheduling. ***
