The purpose of this project is to explore novel embedded processor architectures for electronic textiles (e-textiles). E-textiles are intelligent fabrics where sensors and computation are intrinsic to the cloth, with applications in medicine, entertainment, and sports. E-textiles occupy an extremely constrained point in the embedded system design space, having a large number of networked sensors and processors distributed throughout the fabric and tight requirements on performance, energy consumption, and reliability.
Research at the Virginia Tech E-textiles Lab has shown that a Model-Driven Engineering (MDE) approach allows designers to effectively manage the complexity of the e-textile design space, which includes issues such as fiber selection, the weave pattern, the physical topology of the electrical/communication network in the fabric, the number/type/location of sensor/actuator nodes, the number and type of computational nodes, the system software organization, and the application algorithms.
However, an MDE approach does not yield an implementation that is easily portable while being power- and performance-efficient, due to a fundamental mismatch between the MDE design specification and the target microprocessors. The approach in this project is to develop an event-driven computer architecture family that presents an abstraction that is well-matched to the MDE design specification.
The potential benefits of this project include using the architecture family to improve the reliability, design cost, and energy efficiency of embedded systems besides e-textiles. The broader impacts of the project include e-textile applications in medical monitoring, wearable computing, and pervasive computing. Educational benefits include providing undergraduate and graduate students with multidisciplinary research experience.
The overall objective of this project was to develop a processor architecture that is designed to replace commercial microcontrollers for certain embedded applications, including electronic textiles (e-textiles). This new architecture has several advantages over commercial microcontrollers, including improved energy efficiency, fewer execution cycles, reduced die size, and predictable execution and performance characteristics. The architecture is parameterizable, allowing a family of chips to be created, where each chip would be targeted to a specific class of embedded applications. During the project, we created a parameterizable System Verilog representation of the architecture. This representation was simulated to ensure that the representation was correct. In addition, using commercial CAD tools and a standard cell library, the representation was synthesized and detailed power and execution time results were evaluated. Tools were created to automate this process to allow the automatic exploration of the parameterized design space. The new architecture does not have an instruction set; instead, it is configured to perform a particular computation at runtime. This configuration is generated from a Model-Based Design environment such as the Mathworks Simulink environment. We created software tools that automatically extracted information from the Simulink model files and created the configuration information for the architecture. During the course of this project, several undergraduate and graduate students were employed on the project. Four Master's theses were written. Those four students have graduated and were hired by Intel, Microsoft, and iDirect.
