As multi-core/many-core processors are on the technology roadmap of almost every major microprocessor and embedded-processor vendor today, applications can no longer count on increasing clock rate to improve their performance. They must exploit various forms of parallelism (e.g. thread-level, data-level, and/or memory-level) to achieve improved performance. In the mean time, processors are facing the well-known power wall, instruction-level parallelism (ILP) wall and memory wall that are likely to be exacerbated in the future. Static compilers have been one of the major contributors to dealing with all those challenges. However, they lack runtime information to be used to address possible interactions among tasks competing for the same resources. In addition, operating systems and middleware often incur too much overhead for some forms of parallelism to be effectively used at runtime.
Dynamic runtime optimizers have proven to be capable of dealing with many runtime issues such as memory optimizations on single-core processors. They incur minimal amount of runtime overhead and yet are able to explore useful runtime behavior to re-optimize binary code and re-adapt its execution to achieve higher performance or more efficient power/thermal management. This project researches and develops a dynamic runtime optimizer for multi-core/many-core processors. Such an optimizer requires an infrastructure with several major components each with new approaches and techniques that are different from what are currently used for single-core processors. In this project, a set of benchmarks will be statically compiled and annotated to exploit various forms of parallelism, including speculative threads generated by a research parallelizing compiler that explores thread-level speculation.
