Design for Test (DFT) techniques improve access to the internal state of hardware devices either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand, from a security perspective, hardware devices should minimize the controllability and observability of the internal state to a minimum and thereby minimize/eliminate access to sensitive on-chip information. The sensitive information that needs to be protected may include secret keys stored on cryptographic devices, valuable Intellectual Property incorporated into designs and security software running on general purpose processors.
Intellectual merit: The security vulnerabilities introduced by traditional DFT techniques in a variety of devices including cryptographic hardware, embedded processors running security software and hardware devices that contain valuable intellectual property will be investigated. Not all DFT techniques may introduce security vulnerabilities. Even a given DFT technique may not introduce security vulnerabilities in all chips and in all embedded processors. For example, in large chips and processors with over tens of thousands of flip flops, test data is typically compressed on chip. This in itself makes the task of an attacker quite difficult nay impossible. However, in embedded processors and crypto accelerators used in low end smart cards, test data is not compressed owing to the limited number of flip flops. We will systematically characterize the vulnerabilities by accounting for these factors. The DFT mechanisms that improve testability without compromising security will also be investigated. The PIs will also study the interaction and trade-offs between Testability and Security by understanding the side channels introduced by popular Scan DFT and its variants such as scan with on-chip compression and decompression circuitry and develop security-aware DFT techniques such as secure-scan and encrypted-scan. Finally, the proposal will validate the security-aware DFT techniques by launching DFT-based attacks that they were vulnerable to and by evaluating the resulting testability.
Broader impacts: This research will bring the benefits of smartcard and implantable biomedical electronic devices without compromising their financial and medical security to the general population. The research will demonstrate that security is an important design metric of any design and not just security hardware. This research will play a prominent role in the education of graduate and undergraduate students at Polytechnic and at University of Illinois. The PIs will introduce security aware test in a graduate project oriented courses. Outstanding undergraduates will participate in projects related to this project as part of an undergraduate Senior Design Project for Computer Engineering sequence. At University of Illinois, the PI will reform a sequence of courses to focus on secure embedded system design.
