The objective of this research is to design, fabricate, assemble, characterize, and test innovative compliant, free-standing, parallel-path, off-chip interconnects for next-generation microelectronic systems. The proposed interconnects will be wafer-level, scalable, cost-effective, environmentally-friendly, and reworkable. The approach is to employ a heterogeneous architecture that combines both column and parallel-path compliant interconnects that will be fabricated through sequential lithography and plating processes. By developing electrical and thermo-mechanical simulation models, the interconnect design will be optimized.
The proposed compliant interconnects represent a paradigm shift in chip-to-substrate interconnect technology and present an innovative approach to meet the semiconductor packaging requirements for the year 2016 and beyond. Combining the fundamental principles related to material, mechanical, electrical, and thermal characteristics with practical aspects of fabrication, assembly, and testing of interconnects, this high-risk far-reaching approach proposed in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research.
Through miniaturization, this program will have a unique impact in areas such as high-speed computing, medical electronics and sensors implanted in the body for health monitoring and drug delivery, integrated digital-RF-opto systems, wireless and portable electronics, and smart "fly" electronics and sensors used for intelligence gathering and bio/chemical sensing. Thus, by impacting computer, communications, consumer, and medical microsystems, this research will provide extensive benefits to the society at large. The research findings will be integrated into classroom instruction and published in journals and conferences. Through student internships and one-to-one mentoring, a diverse mix of students will be motivated to pursue engineering education.
