The objective of this research is to develop scalable and robust system- and circuit-architectures to realize highly reliable, power-aware wireline communication networks. The proposed approach takes a holistic view of the entire communication system to develop system-level dynamic power management techniques along with highly scalable, robust, digitally-assisted circuit architectures to improve the energy efficiency of communication links. More than an order of magnitude improvement is to be expected.
The intellectual merit of this research is in the development of (1) a system-level design paradigm to improve energy-efficiency of communication links by more than an order of magnitude, and (2) digitally-assisted circuit architectures that are immune to process variability, transistor imperfections in highly-scaled technologies, and operation in hostile system-on-a-chip environments. The proposed techniques are applicable to links at all levels of the communication hierarchy and are independent of the transmission media and circuit implementation technology.
The broader impacts of this research include lowering the energy and infrastructure costs of communications networks of all sizes ranging from small on-chip networks to large data centers. Such energy savings not only give a competitive edge to the US in the global consumer electronic markets but also will help reduce the detrimental impact of large energy consumption on the environment. The proposed effort also increases the participation of students from under-represented groups through active recruitment, retention, and outreach activities conducted in collaboration with the Women & Minorities in Engineering program at the Oregon State University.
