9634217 Hu This project proposes a dynamic threshold MOS (DTMOS) technology which will permit CMOS circuits to operate at drain voltages at and below 0.5V. Reduction of power supply voltage is critical to low-power operation of scaled CMOS circuits. The DTMOS device is accomplished through and innovative but simple silicon on insulator (SOI) technology. The proposed devices are compatible with existing CMOS circuit architectures. Research is proposed in the study of device technology, physics, modeling and electrical characterization of test circuits. ***
