This Small Business Innovation Research Phase I project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional integrated memory (3DIM) architecture achieved using a single substrate without the need for attaching multiple die together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, each device will scale to smaller dimensions as IC technology continues to progress towards smaller feature sizes without reducing the current through the device, thereby resulting in a dense memory array architecture with signal-to-noise ratio that will improve for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with a diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.
The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, hand-held, mobile internet and other portable devices using non-volatile memory. Materials exhibiting two-terminal, electronically-programmable conductance can potentially impact numerous commercial markets including flash and embedded memory, and will offer orders of magnitude more data storage density as currently-available memory technologies. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate two substrates and bond them together, thereby greatly simplifying the fabrication process, reducing manufacturing cost and increasing product yield. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and much faster than competing technologies. In addition to portable devices, the proposed 3D device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and high-energy proton radiation. Additional testing in planned for other radiation types.
The SiO2-based memory device developed in the Phase I project uses materials commonly found in conventional integrated circuit manufacturing, is smaller than a single transistor and can be formed either in the interconnect layers of an integrated circuit or in the layers used to make transistors. The devices are controlled using electrical signals rather than thermal or chemical energy, making them more power efficient and faster than competing technologies. The benefits of the silicon oxide memory include: direct insertion of memory device into commercially-available integrated circuit technology; fast switching speed; programming voltages comparable to state-of-the-art FLASH memory; high conductance dynamic range; and preliminary data indicating thermal tolerance, long-term data retention and high cycle lifetime. Furthermore, the memory element is a two-terminal device so that only two control lines are needed as opposed to three lines as required for conventional memory cells. The nonvolatile nature of the device allows data to be stored in the array with zero power, making it suitable for FLASH memory applications. In addition, the crossbar architecture can be implemented with only a single diode as an isolation element, compared to the need for 6 to 8 transistors in conventional memory cells. The result is a low-power, nonvolatile memory array with inherent high density as compared to conventional technologies. A method to incorporate two-terminal, electrically-controlled memory at the integrated circuit level with size comparable to a single transistor is highly desirable from a commercial perspective. The memory elements would act as passive, nonvolatile components requiring little power during operation and no power when system power is turned off. Availability of such components could lead to many applications in a broad range of technology areas. PrivaTran has identified a viable integration approach for manufacturing prototype devices in a commercial foundry using existing technology with no changes to the materials, layer thicknesses or process flow. Products and Publications Products from the Phase I project include design and physical layout documentation describing the integration of the nonvolatile memory cell with conventional transistors. Additional Information Scientific and engineering results and data analyses generated by the Phase I project will be reported at technical conferences and in peer-reviewed journals as they are verified in subsequent project phases.
