Non-volatile data storage devices, particularly those based upon NAND flash memory and emerging phase-change memory (PCM) technologies, are revolutionizing the way we access and manipulate information. They have many attractive features compared to magnetic hard disk drives, including their compactness, shock resistance, and faster data access. Flash memory is now preferred in portable consumer electronics, and high performance solid-state drives (SSDs) are being introduced in mobile computing, enterprise storage, data warehousing, and data-intensive computing applications. Accordingly, there is a surge in interest in the refinement, development, and expanded commercial use of these non-volatile memory technologies. On the other hand, these technologies present major challenges in the areas of device reliability, endurance, and energy efficiency. These challenges can be overcome, in part, through innovative coding and data handling techniques, which is the subject of this research project. Specifically, the problems addressed include: (1) the design of efficient, error-resilient rewriting codes for single-level cell (SLC) flash memories using write-once memory (WOM) coding techniques; (2) the design of non-binary rewriting codes for multi-level cell (MLC) flash memories, as well as codes that tolerate asymmetric cell-level transitions and writing errors; (3) the development of coding techniques that mitigate the effects of heat accumulation in PCMs; and (4) the design of error-correcting codes for PCMs with stuck cells.

The research involves the information-theoretic analysis of flash memory and PCM channel models, the development of novel coding schemes, and system performance evaluation. A unique aspect of the project is the use of the facilities of the Non-Volatile Systems Laboratory at UC San Diego, providing an experimental platform for device characterization and empirical performance comparisons of new coding techniques and architectures.

Project Report

Non-volatile data storage devices, particularly those based upon NAND flash memory and emerging phase-change memory (PCM) technologies, are revolutionizing the way we access and manipulate information. They have many attractive features compared to magnetic hard disk drives, including their compactness, shock resistance, lack of moving parts, and lower data-access time. Flash memory is now the storage medium of choice in portable consumer electronic applications, and high performance solid-state drives (SSDs) are also being introduced into mobile computing, enterprise storage, data warehousing in the cloud, and data-intensive computing systems. Accordingly, there is a surge in interest in the refinement, development, and expanded commercial use of these non-volatile memory technologies. On the other hand, these technologies present major challenges in the areas of device reliability, endurance, and energy efficiency, several of which were addressed in this project as summarized below. Flash memory cells consist of floating gate transistors, in which the amount of trapped charge determines the cell voltage, referred to as the cell level. A flash memory cell is written to, or "programmed," by applying a suitable voltage to the cell in order to inject the desired amount of charge to reach a certain cell level. The number of valid cell levels determines the number of bits of information stored in the cell. Programming accuracy and speed directly affect data integrity and device efficiency. One of the most conspicuous properties of flash memory cells is the asymmetry in the programming process. Cell levels can be easily increased by injecting additional charge into them. In contrast, to decrease the level of even a single cell, the whole block of cells (about one million cells) containing it has to be erased and then reprogrammed accordingly. These block erasures not only introduce significant latency into the writing process, but also degrade the floating gate cells, thereby shortening the usable lifetime of the device. Therefore, it is desirable to reduce the number of these block erasures in order to enhance the endurance of the flash memory and increase its lifetime storage capacity. Flash memories also suffer from inter-cell interference (ICI), caused by the parasitic capacitance between adjacent cells, as a result of which the voltage level of a so-called victim cell may be increased when a high voltage is applied to neighboring cells. Over time, charge leakage can cause the cell levels to decrease. These and other phenomena can lead to errors when information stored in the memory is read back. This project tackled these technological problems through the experimental characterization of flash memory error mechanisms, the invention of efficient cell programming algorithms, and the design of enhanced data encoding techniques that are robust to the dominant forms of errors. Specifically, we developed and analyzed parallel programming algorithms that improve the accuracy and speed of writing to multiple cells using standard and "rank modulation" data formats. We developed rewriting codes that represent data in such a way as to permit the reuse of flash memories over multiple, independent write operations without requiring a block erasure. By experimental error analysis, we identified the programmed data patterns that are most susceptible to ICI, and we showed that constrained modulation codes can efficiently eliminate these patterns while, in addition, combating the effects of cell leakage when used in conjunction with dynamic read thresholds. Although these new methods reduce the number of errors encountered during data recording and retrieval, there remains a need for efficient error correction coding techniques to guarantee the complete integrity of the data storage process. To that end, we designed, analyzed, and evaluated a variety of powerful error correction codes that offer practical trade-offs between error-resilience, redundancy, and implementation complexity. We also showed how rewriting capability can be combined with error-correction and ICI-mitigation properties. Empirical performance evaluation and comparison of many of these coding methodologies was carried out using our error measurement platform. The research component of this project introduced new concepts and methods to the scientific disciplines of information theory, coding theory, and mathematics, while contributing to advanced engineering solutions for future solid-state memory technologies. The educational component of the project provided professional training and career-enhancing experiences for student participants, including members of under-represented groups. Upon graduation, several of these students have found employment in the data storage industry. Products of the research have been disseminated widely through publications, presentations, and participation in conferences and workshops sponsored by technical societies, industry consortia, and academia. Together, these activities have contributed substantially to continued U.S. leadership in the vital economic arena of data storage systems and technology.

Project Start
Project End
Budget Start
2011-09-01
Budget End
2014-08-31
Support Year
Fiscal Year
2011
Total Cost
$500,000
Indirect Cost
Name
University of California San Diego
Department
Type
DUNS #
City
La Jolla
State
CA
Country
United States
Zip Code
92093