As more components are packed on to an integrated circuit, a larger amount of heat is generated per unit area, placing strong demands on heat removal mechanisms that transmit this heat to the environment and keep the chip cool. Trends show that under today's design practices and the current economic model for packaging costs, on-chip temperatures will rise from one technology generation to the next. The resulting thermal stresses will degrade the reliability and performance of the circuit, and can result in unacceptable levels of unpredictability in the speed and power of a chip. Current-day techniques use a variety of simple approaches that control the power dissipation of the circuit rather than its temperature, but these will not scale well to future technologies, particularly since the thermal problem is projected to become even more acute as chips are further miniaturized. It is now imperative to consider temperature as a first-class design objective, and this is the goal of this research. There are two aspects to the proposed work: first, simulation techniques will be developed to determine the on-chip temperature distribution, and second, optimization methods for reducing the effects of these variations will be researched.
This work supports the US semiconductor industry by enabling the continued progress along the Moore's law curve, and the research activities will help train students in this field. Moreover, some general purpose simulation/solution techniques developed in this research could have an impact beyond the field of integrated circuits, since these problems frequently arise in numerous other contexts in science and engineering.
