Interconnect has always been the dominant component consuming area, delay, and energy in Field-Programmable Gate Arrays and related spatial computing devices. With interconnect requirements scaling faster than linearly in device gate capacity and fundamental interconnect delays in VLSI scaling slower than gate speeds, this problem is only exacerbated as we go forward. Further, with the size of silicon systems we can build today, all kinds of single-chip architectures (e.g. multiprocessor, system-on-a-chip, VLIW, Vector, PIM) will be moving toward greater on-chip parallelism and hence greater use of on-chip, programmable interconnect.
Nonetheless, interconnect is probably the least understood component in programmable devices. The fundamental goal of this research is to close gaps in our understanding of interconnect structures and in our quantification of interconnect requirements and synthesize this understanding into an engineering-grade approach to programmable interconnect design. This effort will build upon results in VLSI and Parallel theory, but goes beyond them to close asymptotic gaps, understand how to optimize the constant factors, and characterize the properties and behavior of typical designs.
The pedagogical goal is to make the design space, issues, tradeoffs, and impact of spatial interconnect design accessible to students and practitioners with an undergraduate computer science background.
