This research builds on previous studies of shared-memory multiprocessors by using the IEEE proposed Scalable Coherent Interface as a research platform. Multiprocessor issues are studied both at the logical level and the cache coherence level. Important problems at the logical level include study of the performance of a single SCI ring as well as multiple rings, the properties of pipelined networks, and appropriate topologies for connecting simple rings together to create large-scale systems. Important problems at the cache coherence level include enhancements to the shared-memory model to provide for efficient synchronization, extensions to the SCI coherence protocol and the benefit of relaxing event ordering constraints in the memory system.
