This research is on interconnect design in submicron technologies, with the goal of developing a logic synthesis methodology which would produce highly regular layout structures without large area penalty. Research issues being explored include: the relationship between circuit structure and its incremental restructurability; achieving a network of given properties through a sequence of incremental changes; simultaneous switching and cross-talk noise effects in RC interconnects; accurate, easy to compute bounds on crosstalk amplitude and duration; modeling the influence of crosstalk on delay; design optimization techniques for minimizing crosstalk effects in synthesis; and modeling of low-level effects which can be corrected at the routing/wire sizing and/or transistor sizing steps. The project is also developing a methodology to determine crosstalk budgets based on circuit structure, as well as transistor and wire sizing tools which will consider both crosstalk and delay. Techniques for buffer insertion and spacing, net reordering, and Boolean level regularity are also being investigated.
