The goals of this research are to (a) develop new ways of placing high-quality few-layer graphene on entire device active areas over a large wafer, by a graphene-on-demand approach that precisely cuts, selects and transfer-prints (GCST) high-quality graphene from graphite onto the wafer, and (b) as a test bed for GCST, scale and develop new graphene FET structures, materials, and fabrication technologies for IC integration. The research is based on the Principal Investigator groups recent successful demonstration of the most critical steps of Principal Investigator groups GCST approach: precisely cutting, exfoliating and transfer-printing (with a stamp) of 3-6 monolayer thick graphene from bulk graphite to device active areas of another substrate; and successful fabrication of high performance FETs using GCST-printed graphene that have FET mobility and on drive current that are among the highest demonstrated. The research also relies on Principal Investigator groups previous extensive work in nanopatterning (including nanoimprinting and transfer-patterning) and nanoscale Si MOSFETs. The research is to further develop these successes and make other innovations that are necessary to achieve the goals.
The research will generate new cutting-edge knowledge in new nanofabrication technologies, new materials, and graphene FETs, and will have broad applications in future nanomanufacturing and next generation electronics. Thus, the success of the research will benefit U.S.'s competitiveness in nanotechnology, aid U.S. industry, and will potentially have significant economic impact. The research will train graduate and undergraduate students in the new technology area of nanofabrication and nanoelectronics.
